This invention relates to a semiconductor memory device such as a synchronous dynamic random access memory (DRAM) and, in particular, to control a state of data readout routes through which data are read out from memory cells.
With a recent development of a micro processing unit (MPU), there arises a strong demand for a semiconductor memory device of a high speed. As one approach therefor, proposal has been made of a synchronous DRAM which is operable in synchronism with an external clock supplied from an external source.
In the manner which will later be discussed in detail with reference to a drawing, a conventional synchronous DRAM comprises a period determining arrangement, a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a first processing arrangement, a plurality of read bus pairs, and a second processing arrangement. The period determining arrangement is for determining a burst period. The word lines are connected to the memory cells. The bit line pairs are connected to the memory cells. Each of the bit line pairs comprises two bit lines having a bit line potential difference therebetween. The first processing arrangement is connected to the bit line pairs and is for processing the bit line potential difference into a first difference signal. The read bus pairs are connected to the first processing arrangement and supplied with the first difference signal. Each of the read bus pairs comprises two read buses having a read bus potential difference therebetween. The second processing arrangement is connected to the read bus pairs and is for processing the read bus potential difference into a second difference signal.
The conventional synchronous DRAM further comprises a precharge circuit for carrying out a precharge operation to precharge each of the read bus pairs in response to necessity in the manner known in the art. In the precharge operation, each of the read bus pairs is electrically charged, amplified, and discharged in every one cycle having a cycle time. This results in a large consumption of charging/discharging current of each of the read bus pairs. Particularly when the cycle time is shortened, the charging/discharging current generates a noise on a power supply line and on a ground line in the manner known in the art.
Another prior art example is disclosed in Japanese Patent Prepublication (Kokai or Publication of Unexamined Patent Application) No. 294991/1990. In the prior art example, selected ones of data readout routes are continuously and electrically charged for a predetermined time period. However, it is impossible to apply the prior art example to a case where the data readout routes are connected to a ground line or an earth line through a direct current path in the manner known in the art.